For example: Adding: Figure 1: Block diagram of BCD adder When an output carry K = 0 nothing happens as the out S8S4S2S1 is added to 0000 in the second 4-bit adder, but when K=1 OR Z8&Z4 OR Z8&Z2 is equal to ‘1’, the output carry generates a ‘1’, thus “0110” is added to the output of the first 4-bit adder. The gives the expression for correction requirement: Cor = K + Z8Z4 +Z8Z2 When Cor = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next stage. Point where binary sum has output carry K =1 or, 2. The conditions for the levels on the table where correction is required a 1. Bellow the ruled level on the table, the BCD adder should detect that the binary codes are unusable in BCD coding system and provide the necessary correction. The K and C in the table are the respective binary carry and BCD carry bits. The table bellow shows decimal numbers 0-19 with their corresponding binary and BCD codes. Consider adding 9+9+1 in decimal, the result is 19, in straight binary this should produce an output 100112, this is an invalid number in BCD, because in BCD code the group of four bit binary only represent decimal numbers 0-9. The four bit sum output and the output carry represents the five outputs. In this article I’ll analyse and design a BCD adder which requires a minimum of nine inputs and five outputs, four bits are require to code the aguend and the addend making eight bits, and the circuit input carry makes the nine inputs. To enhance Computer-Human relationship in this perspective, arithmetic operations are performed by the computer in a binary coded decimal, (BCD) form. Verilog code for BCD Adder: module bcdadd(a,b,cin,s,cout) //Main module of one digit BCD adder input a input b input cin outputs output cout wire w wire y,c0,c1,c2,c3,c4,c5 fulladd m1(a,b,cin,w,c0) fulladd m2(a,b,c0,w,c1) fulladd m3(a,b,c1,w,c2) fulladd m4(a,b,c2,w,c3) assign y=c3|(w&(w|w)) halfadd m5(w,y,s,c4) fulladd m6(w,y,c4,s,c5) halfadd m7(w,c5,s,cout) assign s=w endmodule module fulladd(a,b,cin,s,cout) //submodule for fulladder input a,b input cin output s output cout wire w1,w2,w3 halfadd g1(a,b,w1,w2) halfadd g2(w1,cin,s,w3) assign cout=w3|w2 endmodule module halfadd(a,b,s,cout) //submodule for halfadder input a,b output s,cout assign s=a^b assign cout=a&b endmodule BCD Adder design and simulation with Verilog HDL Code in ModelSim Computers understand binary number system while humans are used to arithmetic operations in decimal number systems.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |